1. Field of the Invention
The present invention relates to an electro-optical device such as an image display device and an image capturing apparatus and more particularly, to a scanning line drive circuit only composed of a same conductivity type field-effect transistor, and a shift register circuit used therein.
2. Description of the Background Art
An electro-optical device having a scanning line drive circuit to scan pixels connected to a scanning line has been widely known. For example, an image display device (referred to as the “display device” hereinafter) such as a liquid crystal display device is configured such that a gate line (scanning line) is provided with respect to each pixel row (pixel line) of a display element (display panel) in which a plurality of pixels are arranged in a form of a matrix, and a display image is updated by sequentially selecting and driving the gate line every horizontal period of a display signal. The gate line drive circuit (scanning line drive circuit) to sequentially select and drive the pixel line, that is, the gate line employs a shift register to perform a shift operation which goes through a cycle for one frame period of the display signal.
In addition, pixels of the imaging elements used in the image capturing apparatus are also arranged in the form of a matrix, and data of a taken image is extracted when the gate line drive circuit scans those pixels. The shift register can be used in the gate line drive circuit of the image capturing apparatus.
The shift register used in the gate line drive circuit is desirably composed of only the same conductivity type field-effect transistor to reduce the number of steps in a production process of the display device. Therefore, various kinds of shift registers composed of only an N-type or P-type field-effect transistor and display devices having them are proposed (in the following Japanese Patent Application Laid-Open Nos. 2000-347628, 2004-78172, 2007-257813, and 2008-287753, for example).
The shift register serving as the gate line drive circuit is composed of a plurality of cascaded shift register circuits each provided in one pixel line, that is, one gate line. In this specification, each of the shift register circuits constituting the gate line drive circuit is referred to as the “unit shift register”.
Japanese Patent Application Laid-Open No. 2000-347628 discloses a gate line drive circuit in which a stage (odd driver) to scan pixels in odd rows of multi-stage shift registers, and a stage (even driver) to scan pixels in even rows thereof are arranged so as to sandwich a display element or an imaging element. When the odd driver and the even driver are arranged in such a manner, a region for the gate line drive circuit can be efficiently used.
FIGS. 3 and 4 of the above document show a unit shift register used in the gate line drive circuit and a signal waveform thereof, respectively. In FIG. 3, a start signal IN inputted to a unit shift register RSlo (1) in a first stage of an odd driver 2o is temporally shifted by the unit shift register RSlo (1) and outputted as a selection signal OUT1 of a gate line GL1 of a first row of a liquid crystal display element. The selection signal OUT1 is inputted to a unit shift register RS1e (1) in a first stage of an even driver 2e through the gate line GL1 and temporally shifted by the unit shift register RSle (1), and outputted as a selection signal OUT2 of a gate line GL2 of a second row. The same operation is performed in the unit shift registers in the following stages, so that the gate lines are sequentially selected.
As shown in FIG. 3 of the above document, although the unit shift register in each stage has the same circuit configuration, here, attention is paid to the unit shift register RS1e (1) in the first stage of the even driver 2e. The selection signal OUT2 outputted from the unit shift register RS1e (1) is activated when a clock signal/CK is transmitted to an output terminal by a transistor 204 which is turned on in response to activation of a selection signal OUT of the previous stage (unit shift register RS1o(1)).
While the transistor 204 is turned on when wiring capacitances C2 and C4 of its control electrode is charged by the selection signal OUT1, the selection signal OUT1 outputted from the previous stage is supplied to the unit shift register RS1e(1) through the gate line GL1, so that it is affected by a resistance component and a capacitance component of the gate line GL1. That is, rising speed of the selection signal OUT1 decreases in proportion to a time constant based on the product of a sum of the resistance components and a sum of the capacitance components (this is described in paragraph 0043 in Japanese Patent Application Laid-Open No. 2004-78172).
As a result, since charging speed of the control electrode of the transistor 204 slows down, there is a concern that the control electrode of the transistor 204 is not sufficiently charged when the shift register is operated at high speed. When the control electrode of the transistor 204 is not sufficiently charged, on-resistance of the transistor 204 increases, and charging speed of the output terminal, that is, rising speed of the selection signal OUT2 decreases.
The selection signal OUT2 is supplied to the next stage (unit shift register RS1o (2) of the second stage in the odd driver 2o) through the gate line GL2 and affected by a resistance component and a capacitance component of the gate line GL2 at this time, so that its rising speed further decreases.
When this phenomenon is repeated every time the selection signal is sequentially transmitted to the unit shift register in each stage, the rising speed decreases as the selection signal goes through the latter stages, and the selection signal could not be activated in the middle stage and the selection signal could not be transmitted to the final stage. This problem arises prominently in an electro-optical device having a long gate line such as a display device having a large screen.